1. Field
The present technology relates to semiconductor packaging.
2. Description of Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated from so-called 3-D semiconductor devices, including for example a system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate in a stacked configuration. Edge views of conventional 3-D semiconductor packages 20 (without molding compound) are shown in prior art FIGS. 1 and 2. Typical packages include a plurality of semiconductor die 22 mounted to a substrate 26. In the examples shown, the die stack has four die, 22a, 22b, 22c and 22d. Further examples have more or less die in the stack. Although not shown in FIGS. 1 and 2, the semiconductor die 22 are formed with die bond pads on an upper surface of the die. Substrate 26 may be formed of an electrically insulating core sandwiched between upper and lower conductive layers. The upper and/or lower conductive layers may be etched to form conductance patterns including electrical leads and contact pads. Wire bonds 30 are soldered between the die bond pads of the semiconductor die 22 and the contact pads of the substrate 26 to electrically couple the semiconductor die to the substrate. The electrical leads on the substrate in turn provide an electrical path between the die and a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
It is known to stack semiconductor die 22 on top of each other either with an offset configuration (prior art FIG. 1) or in an aligned configuration (prior art FIG. 2). In the offset configuration of FIG. 1, the die 22 are stacked with an offset so that the bond pads of the next lower die are left exposed. Such configurations are shown for example in U.S. Pat. No. 6,359,340 to Lin, et al., entitled, “Multichip Module Having a Stacked Chip Arrangement,” which patent is incorporated herein by reference in its entirety. An offset configuration provides an advantage of convenient access to the bond pads on each of the semiconductor die. However, the offset requires a greater footprint on the substrate, where space is at a premium.
In the aligned configuration of prior art FIG. 2, the semiconductor die 22 are stacked directly on top of each other, thereby taking up less footprint on the substrate as compared to an offset configuration. However, in an aligned configuration, space must be provided between adjacent semiconductor die for the bond wires 30. In addition to the height of the bond wires 30 themselves, additional space must be left above the bond wires, as contact of the bond wires 30 of one die with the next die above may result in an electrical short. As shown in FIG. 2, it is therefore known to provide a dielectric spacer layer 34 to provide enough room for the bond wires 30 to be bonded between adjacent die 22. The requirement of the spacer layer adds height to the die stack and is a limiting factor in the number of die which may be included in the stack to still fit within the height of a standard memory card form factor.
Given the constant drive for greater storage capacity within a semiconductor package conforming to standard memory card form factors, there is a need for a new memory die packaging design.